High-performance computer or microprocessor systems, such as a floating point processor (FPP) that might be used, for example, in a graphics chip set, may require the execution of 64-bit instructions. At present, execution of 64-bit instructions may be implemented either by the use of a cache memory (or a memory system) characterized by 64-bit width or by performing multiple fetches of 32-bit instructions for each execution of an instruction.
Parallel execution from a 64-bit wide cache requires that the instruction conform to, or be aligned on, even 64-bit boundaries. This approach can result in wasted cache and memory.
On the other hand, performing double fetches requires an instruction memory that operates at a speed twice that of the execution pipe. As is well known, fast semiconductor memory is expensive.
Accordingly, the subject invention realizes an advance in the state of the art by providing two execution pointers for use with an interleaved instruction cache. The dual pointers are alternately incremented for non-parallel operation and are simultaneously incremented for parallel operation. This inventive technique enables 64 bits of instruction data to be called for execution during each clock cycle, but permits either 32 or 64 bits to be executed depending on the instruction definition.